4,199
edits
Changes
From IGEP - ISEE Wiki
no edit summary
| SYS_CLKOUT1(mode=0)
| Configurable output clock1
| GPIO_10(mode=4)<br>SAFE_MODE(mode=7)
| -
|-
| SYS_NIRQ(mode=0)
| External interrupt
| GPIO_0(mode=4)<br>SAFE_MODE(mode=7)
| TPS65950:CONTROL
|-
| I2C3_SDA(mode=0)
| I2C3 Interface
| GPIO_185(mode=4)<br>SAFE_MODE(mode=7)
| J5
|-
| I2C3_SCL(mode=0)
| I2C3 Interface
| GPIO_184(mode=0)<br>SAFE_MODE(mode=7)
| J5
|-
| GPIO_186(mode=4)
| -
| SYS_CLKOUT2(mode=0)<br>SAFE_MODE(mode=7)
| -
|-
| UART2 Clear to send
|
MCBSP3_DX(mode=1)<br>GPT9_PWM_EVT(mode=2)<br>GPIO_144(mode=4)<br>SAFE_MODE(mode=7)
| -
| UART3_CTS(mode=0)
| UART3 Clear to send
| GPIO_163(mode=4)<br>SAFE_MODE(mode=7)
| -
|-
| UART3_TX(mode=0)
| UART· transfer data
| GPIO_166(mode=4)<br>SAFE_MODE(mode=7)
| -
|-
| UART3_RX(mode=0)
| UART· Receive data
| GPIO_165(mode=4)<br>SAFE_MODE(mode=7)
| -
|-
| DSS_PCLK(mode=0)
| LCD Clock
| GPIO_66(mode=4)<br>HW_DBG12(mode=5)<br>SAFE_MODE(mode=7)
| -
|-
| DSS_VSYNC(mode=0)
| LCD vertical sync
| GPIO_68(mode=4)<br>SAFE_MODE(mode=7)
| -
|-
| UART2 Ready to send
|
MCBSP3_DR(mode=1)<br>GPT10_PWM_EVT(mode=2)<br>GPIO_145(mode=4)<br>SAFE_MODE(mode=7)
| -
| USB1
|
ETK_D1(mode=0)<br>MCSPI3_SOMI(mode=1)<br>GPIO_15(mode=4)<br>MM1_TXSE0(mode5)<br><font color="red">HSUSB3_TLL_DATA1(mode=6)</font><br>HW_DBG3(mode=7)
| -
