Changes

This workaround can be helpful when your board is not connected to Internetall the time. Using For this method we are going to:

* Rectify systematic clock error using configuring PMIC RTC registers

Every Each IGEP Board has its own systematic clock error. To find guess it, we use Can be helpful use [http://labs.isee.biz/index.php/How_to_adjust_Hardware_RTC_clock#ntpdate__program ntpdate program] to calculate the systematic clock offset error added every day:

* Syncronize Synchronize your system clock using: ntpdate pool.ntp.org* Compare actual offset (it is recommendable wait between one or two days to deprecate random clock errorsproduced by crystal and ntp synchronization): ntpdate -q pool.ntp.org && date

My IGEP Finally, my IGEPv2 RC Board was a systematic drift of +3.6 seconds/day aprox.

=== Rectify systematic clock error using configuring PMIC RTC registers ===