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Peripherals Summary

24 bytes added, 12:48, 1 February 2012
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=== MMC ===
MMC (Multimedia Controller) is peripheral than can manage SD/MMC/[http://en.wikipedia.org/wiki/Secure_Digital#SDIO SDIO] , but other peripherals can be controled with this interface like WlanWIFI. The MMC/SD/SDIO host controller deals with MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRC), start/end bit, and checking for syntactical correctness. Data transfers between the MMC controller and a memory card can use one bidirectional data line (for the MMC protocol) or four parallel data lines (for the SD protocol). There are three MMC peripherals (MMC1, MMC2 and MMC3) and their use CMOS voltage levels (1V8). It can use ten signals:<br>
There are three MMC peripherals (MMC1, MMC2 and MMC3) and their use CMOS voltage levels (1V8). It can uses ten signals:<br>  *MMC_DAT7: SD/MMC data pin 7.*MMC_DAT6: SD/MMC data pin 6.*MMC_DAT5: SD/MMC data pin 5.*MMC_DAT4: SD/MMC data pin 4.*MMC_DAT3: SD/MMC data pin 3. Used in SD card default data mode.*MMC_DAT2: SD/MMC data pin 2. Used in SD card default data mode.*MMC_DAT1: SD/MMC data pin 1. Used in SD card default data mode.*MMC_DAT0: SD/MMC data pin 0. Used in MMC and SD card default data mode.*MMC_CMD: SD/MMC command signal.
*MMC_CLK0: SD/MMC clock signal.<br>
Some especifications are:
*Full compliance with MMC command/response sets as defined in the Multimedia Card System Specification, v4.2 including high-capacity (size &gt; 2GB) cards HC MMC.*Full compliance with SD command/response sets as defined in the SD Memory Card Specifications, v2.0 including high-capacity SDHC cards up to 32GB.*Full compliance with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v2.00*Full compliance with sets as defined in the SD Card Specification, Part A2, SD Host Controller Standard Specification, v2.00*Full compliance with MMC bus testing procedure as defined in the Multimedia Card System Specification, v4.2*Full compliance with CE-ATA command/response sets as defined in the CE-ATA Standard Specification*Built-in 1024-byte buffer for read or write*32-bit-wide access bus to maximize bus throughput*Designed for low power*Programmable clock generation*Support SDIO Read Wait and Suspend/Resume functions
*Support:
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - 1-bit or 4-bit transfer mode specifications for SD and SDIO cards
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards
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