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= Overview =
This article pretends introduce the capabilities of most used peripherals in IGEPv2, with a brief explanation and program examples to make easy to learning it. For more detailed information see this [http://www.ti.com/litv/pdf/spruf98u manual].<br>
= Feedback and Contributing =
[http://omappedia.org/wiki/Kernel_UART http://omappedia.org/wiki/Kernel_UART]
[[How to use UARTs]]
=== GPIO ===
- Set the data input and output direction<br>- Configure GPIO pin to high or low states.<br>- Configure GPIO pins for interrupt control<br>- Enable and disable interrupts<br>- Enable and disable wakeup capability per GPIO pin.
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More information:
- [http://omappedia.org/wiki/GPIO http://omappedia.org/wiki/GPIO]
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[[How to use GPIOs]] Example: [[What can I do with IGEP0020#How_to_handle_the_gpio-LED.27s]]
=== SPI ===
Omap McSPI have the next caractheristics:
- Supports DMA for data transfer operations, for reduce CPU usage. <br> - Supports full duplex data transfer operations, <span lang="en" classid="short_textresult_box" idclass="result_boxshort_text"><span class="hps">simultaneous comunication between master and slave.</span></span><br> - Supports configuration of number of wordlength. <br> - Supports configuration of phase and polarity of the device functional clock for each channel. <br> - Support configuration of the bitrate for each channel. Between 1.5 KHz and 48 MHz
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[[How to use SPI]]
=== BSP ===
- McBSP_DX: Transmited serial data.<br> - McBSP_CLKX: Transmit serial clock.<br> - McBSP_FSX: Transmit frame syncronization.<br> - McBSP_DR: Received serial data.<br> - McBSP_CLKR: Received serial clock. Only in MCBSP1.<br> - McBSP_FSR:Received frame syncronization. Only in MCBSP1.<br> - McBSP_CLKS: External clock (shared by all McBSP modules).<br>
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List of recommended usage (non exhaustive) per McBSP modules in the device:<br>- McBSP1: Digital baseband (DBB) Data<br>- McBSP2: Audio data with audio buffer and SIDETONE feature<br>- McBSP3: Bluetooth voice data with SIDETONE feature<br>- McBSP4: DBB voice data<br>- McBSP5: Midi data
More information:
[http://omappedia.org/wiki/Kernel_McBSP http://omappedia.org/wiki/Kernel_McBSP]<br>
=== MMC ===
MMC (Multimedia Controller) is peripheral than can manage SD/MMC/[http://en.wikipedia.org/wiki/Secure_Digital#SDIO SDIO] , but other peripherals can be controled with this interface like Wlan. The MMC/SD/SDIO host controller deals with MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRC), start/end bit, and checking for syntactical correctness. Data transfers between the MMC controller and a memory card can use one bidirectional data line (for the MMC protocol) or four parallel data lines (for the SD protocol). There are three MMC peripherals (MMC1, MMC2 and MMC3) and their use CMOS voltage levels (1V8). It can use ten signals:<br>
- MMC_DAT7: SD/MMC data pin 7. Used by SDIO.<br>- MMC_DAT6: SD/MMC data pin 6. Used by SDIO.<br>- MMC_DAT5: SD/MMC data pin 5. Used by SDIO.<br>- MMC_DAT4: SD/MMC data pin 4. Used by SDIO.<br>- MMC_DAT3: SD/MMC data pin 3. Used in SD card default data mode.<br>- MMC_DAT2: SD/MMC data pin 2. Used in SD card default data mode.<br>- MMC_DAT1: SD/MMC data pin 1. Used in SD card default data mode.<br>- MMC_DAT0: SD/MMC data pin 0. Used in MMC and SD card default data mode.<br>- MMC_CMD: SD/MMC command signal.<br>- MMC_CLK0: SD/MMC clock signal.<br>
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Some especifications are:
- Full compliance with MMC command/response sets as defined in the Multimedia Card System Specification, v4.2 including high-capacity (size > 2GB) cards HC MMC.<br> - Full compliance with SD command/response sets as defined in the SD Memory Card Specifications, v2.0 including high-capacity SDHC cards up to 32GB.<br> - Full compliance with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v2.00<br> - Full compliance with sets as defined in the SD Card Specification, Part A2, SD Host Controller Standard Specification, v2.00<br> - Full compliance with MMC bus testing procedure as defined in the Multimedia Card System Specification, v4.2<br> - Full compliance with CE-ATA command/response sets as defined in the CE-ATA Standard Specification<br> - Built-in 1024-byte buffer for read or write<br> - 32-bit-wide access bus to maximize bus throughput<br> - Designed for low power<br> - Programmable clock generation<br> - Support SDIO Read Wait and Suspend/Resume functions<br> - Support:<br> - 1-bit or 4-bit transfer mode specifications for SD and SDIO cards<br> - 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards
=== I2C ===
