=== I2C ===
I2C (Inter-Integrated Circuit) is a [http://en.wikipedia.org/wiki/Multi-master_bus multi-master] serial computer bus.<br> There are four I2C in Omap, but only three avaliable (I2C4 is used to comunicate with TPS65950). Omap I2C peripheral use CMOS voltage level (1V() and implements two signals:
Omap I2C peripheral implements two signals- SDA: Data. Open-drain output buffer. Requires external pullup resistor. <br>- SCL: Clock, master device generate it. Open-drain output buffer. Requires external pullup resistor. <br>
- SDA: Data. Open-drain output buffer. Requires external pullup resistor. <br>- SCL: Clock, master device generate it. Open-drain output buffer. Requires external pullup resistor. <br>
There are four I2C in Omap, but only three avaliable (I2C4 is used to comunicate with TPS65950). Their caracteristics are:<br>
- Uses CMOS voltage levels (1V8)Their caracteristics are:<br>- Compliance with Philips I2C specification version 2.1<br> - Support for standard mode (up to 100K bits/s), fast mode (up to 400K bits/s) and HS mode for transfer up to 3.4M bits/s<br> - Support for 3-wire/2-wire SCCB master mode for I2C2 and I2C3 modules, 2-wire SCCB master mode for I2C1 module, up to 100K bits/s<br> - 7-bit and 10-bit device addressing modes<br> - General call<br> - Start/restart/stop<br> - Multimaster transmitter/slave receiver mode<br> - Multimaster receiver/slave transmitter mode<br> - Combined master transmit/receive and receive/transmit mode<br> - Built-in FIFO for buffered read or write:<br> – 8 bytes for I2C1 and I2C2<br> – 64 bytes for I2C3<br> - Module enable/disable capability<br> - Programmable clock generation<br> - 8-bit-wide data access<br> - Low-power consumption design<br> - Two [http://en.wikipedia.org/wiki/Direct_memory_access DMA] channels<br> - Wide interrupt capability<br>
More information:
