Changes

- Full compliance with MMC command/response sets as defined in the Multimedia Card System Specification, v4.2 including high-capacity (size &gt; 2GB) cards HC MMC.<br> - Full compliance with SD command/response sets as defined in the SD Memory Card Specifications, v2.0 including high-capacity SDHC cards up to 32GB.<br> - Full compliance with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v2.00<br> - Full compliance with sets as defined in the SD Card Specification, Part A2, SD Host Controller Standard Specification, v2.00<br> - Full compliance with MMC bus testing procedure as defined in the Multimedia Card System Specification, v4.2<br> - Full compliance with CE-ATA command/response sets as defined in the CE-ATA Standard Specification<br> - Built-in 1024-byte buffer for read or write<br> - 32-bit-wide access bus to maximize bus throughput<br> - Designed for low power<br> - Programmable clock generation<br> - Support SDIO Read Wait and Suspend/Resume functions<br> - Support:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - 1-bit or 4-bit transfer mode specifications for SD and SDIO cards<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards  <br>  <br>  Under construction