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Every Each IGEP Board has its own systematic clock error. To find guess it, we use Can be helpful use [http://labs.isee.biz/index.php/How_to_adjust_Hardware_RTC_clock#ntpdate__program ntpdate program] to calculate the systematic clock offset error added every day:
My IGEP Finally, my IGEPv2 RC Board was a systematic drift of +3.6 seconds/day aprox.
→Rectify systematic error editing PMIC RTC registers
== Rectify systematic error editing PMIC RTC registers ==
This workaround can be helpful when your board is not connected to Internetall the time. Using For this method we are going to:
* Calculate systematic clock error
* Rectify systematic clock error using configuring PMIC RTC registers
=== Calculate systematic clock error ===
* Syncronize Synchronize your system clock using: ntpdate pool.ntp.org* Compare actual offset (it is recommendable wait between one or two days to deprecate random clock errorsproduced by crystal and ntp synchronization): ntpdate -q pool.ntp.org && date
=== Rectify systematic clock error using configuring PMIC RTC registers ===
==== Overview ====
* Check register values:
<pre>i2cdump -y -f 1 0x4b </pre>
More information at [http://www.ti.com/litv/pdf/swcu050g TPS65950 TRM] section 3.4.2
==== Correct system clock ====