Difference between revisions of "OMAP3530"
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| − | = Texas Instruments OMAP3530 | + | =Texas Instruments OMAP3530= |
| + | [http://focus.ti.com/dsp/docs/dspcontent.tsp?contentId=53403 '''[[File:custom_diagram_1_OMAP3530.jpg|100%x274px|center]]'''] | ||
| − | + | '''<u>MPU Subsystem</u>''' | |
| − | + | * Up to 720-MHz [http://www.arm.com/ ARM] [http://www.arm.com/products/processors/cortex-a/cortex-a8.php Cortex™-A8 Core] ARMv7 Architecture. | |
| + | * In-Order, Dual-Issue, Superscalar Microprocessor Core. | ||
| + | * [http://www.arm.com/products/processors/technologies/neon.php NEON™ SIMD Coprocessor] | ||
| − | + | <u>'''High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem.'''</u> | |
| − | |||
| − | |||
| − | + | * 520-MHz [http://focus.ti.com/lit/ug/spru871j/spru871j.pdf TMS320C64x+™ DSP Core] | |
| + | * Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels) | ||
| + | * Video Hardware Accelerators | ||
| − | + | <u>'''POWERVR SGX™ Graphics Accelerator'''</u> (SGX530 [http://www.imgtec.com/ Imagination Technologies]) | |
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| − | |||
| − | + | * Tile Based Architecture delivering 10 MPoly/sec | |
| + | * Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality | ||
| + | * Industry Standard API Support: [http://www.khronos.org/opengles/1_X/ OpenGLES 1.1] and [http://www.khronos.org/opengles/2_X/ 2.0], [http://www.khronos.org/openvg/ OpenVG1.0] | ||
| + | * Fine Grained Task Switching, Load Balancing, and Power Management | ||
| + | * Programmable High Quality Image Anti-Aliasing | ||
| − | + | <u>'''Fully Software-Compatible With C64x and ARM9™'''</u> | |
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| − | |||
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| − | <u>''' | + | <u>'''Commercial and Extended Temperature Grades'''</u> |
| − | <u>''' | + | <u>'''Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core'''</u> |
| − | + | * Eight Highly Independent Functional Units | |
| − | + | [[Image:OMAP3530 bloques.jpg|center]] | |
| − | [ | + | ==Documentation== |
| + | [http://www.ti.com/litv/pdf/spruf98d OMAP3530 Hardware Reference Manual] | ||
| − | == | + | = See also = |
| − | |||
| − | |||
| − | + | * [[TPS65950]] | |
| − | *[[TPS65950]] | ||
[[Category:Features]] | [[Category:Features]] | ||
Revision as of 10:17, 27 February 2018
Texas Instruments OMAP3530
MPU Subsystem
- Up to 720-MHz ARM Cortex™-A8 Core ARMv7 Architecture.
- In-Order, Dual-Issue, Superscalar Microprocessor Core.
- NEON™ SIMD Coprocessor
High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem.
- 520-MHz TMS320C64x+™ DSP Core
- Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
- Video Hardware Accelerators
POWERVR SGX™ Graphics Accelerator (SGX530 Imagination Technologies)
- Tile Based Architecture delivering 10 MPoly/sec
- Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
- Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
- Fine Grained Task Switching, Load Balancing, and Power Management
- Programmable High Quality Image Anti-Aliasing
Fully Software-Compatible With C64x and ARM9™
Commercial and Extended Temperature Grades
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units
Documentation
OMAP3530 Hardware Reference Manual
