Difference between revisions of "IMX6 Solo"

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(Documentation)
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</div>
 
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==<u>Block diagram</u>==
 
==<u>Block diagram</u>==
<div style='padding-left: 150px;'>[[File:Screenshot-2018-4-4_i_MX_6Solo_6DualLite_Applications_Processors_for_Consumer_Products_Data_Sheet_-_IMX6SDLCEC_pdf.png|563x439px]]</div>
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<div style="padding-left: 150px;">[[File:Screenshot-2018-4-4_i_MX_6Solo_6DualLite_Applications_Processors_for_Consumer_Products_Data_Sheet_-_IMX6SDLCEC_pdf.png|563x439px]]</div>
 
==Documentation==
 
==Documentation==
 
* [https://www.nxp.com/docs/en/data-sheet/IMX6SDLIEC.pdf  i.MX 6Solo/6DualLite Applications Processors for Industrial Products]
 
* [https://www.nxp.com/docs/en/data-sheet/IMX6SDLIEC.pdf  i.MX 6Solo/6DualLite Applications Processors for Industrial Products]
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* [https://www.nxp.com/docs/en/reference-manual/IMX6SDLRM.pdf i.MX 6Solo/6DualLite Applications Processor Reference Manual]
 
* [https://www.nxp.com/docs/en/reference-manual/IMX6SDLRM.pdf i.MX 6Solo/6DualLite Applications Processor Reference Manual]
 
* [https://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines]
 
* [https://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines]
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==See also==
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* Dual Lite
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* Dual
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* Quad

Revision as of 09:57, 4 April 2018

NXP i.MX6 Solo

IMX6Solo Diagrama.jpg

CPU Complex

Memory

DDR
  • 32 bit LP-DDR3/LV-DDR3

NAND

  • SLC/MLC, 40-bit ECC, ONFI2.2, DDR

Advanced power management

Block diagram

Screenshot-2018-4-4 i MX 6Solo 6DualLite Applications Processors for Consumer Products Data Sheet - IMX6SDLCEC pdf.png

Documentation

See also

  • Dual Lite
  • Dual
  • Quad