Difference between revisions of "IMX6 Solo"
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* [https://www.nxp.com/docs/en/user-guide/IMX6DQ6SDLHDG.pdf IMX6DQ6SDLHDG, Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors] | * [https://www.nxp.com/docs/en/user-guide/IMX6DQ6SDLHDG.pdf IMX6DQ6SDLHDG, Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors] | ||
* [https://www.nxp.com/docs/en/fact-sheet/IMX6SRSFS.pdf i.MX 6 Series of Applications Processors Fact Sheet] | * [https://www.nxp.com/docs/en/fact-sheet/IMX6SRSFS.pdf i.MX 6 Series of Applications Processors Fact Sheet] | ||
| − | * | + | * [https://www.nxp.com/docs/en/reference-manual/IMX6SDLRM.pdf i.MX 6Solo/6DualLite Applications Processor Reference Manual] |
* [https://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines] | * [https://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines] | ||
Revision as of 09:56, 4 April 2018
NXP i.MX6 Solo
CPU Complex
- 1x ARM Cortex-A9 up to 1 GHz
- NEON SIMD media accelerator
Memory
DDR
- 32 bit LP-DDR3/LV-DDR3
NAND
- SLC/MLC, 40-bit ECC, ONFI2.2, DDR
Advanced power management
Block diagram
Documentation
- i.MX 6Solo/6DualLite Applications Processors for Industrial Products
- i.MX 6Solo/6DualLite Automotive and Infotainment Applications Processors
- i.MX 6Solo/6DualLite Applications Processors for Consumer Products
- IMX6DQ6SDLHDG, Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors
- i.MX 6 Series of Applications Processors Fact Sheet
- i.MX 6Solo/6DualLite Applications Processor Reference Manual
- LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines
