Difference between revisions of "IMX6 Quad"

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* [https://www.nxp.com/docs/en/fact-sheet/IMX6SRSFS.pdf i.MX 6 Series of Applications Processors Fact Sheet]
 
* [https://www.nxp.com/docs/en/fact-sheet/IMX6SRSFS.pdf i.MX 6 Series of Applications Processors Fact Sheet]
 
* [https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf i.MX 6Dual/6Quad Applications Processor Reference Manual]
 
* [https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf i.MX 6Dual/6Quad Applications Processor Reference Manual]
* [https://www.nxp.com/docs/en/engineering-bulletin/EB821.pdf LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines]
 
  
 
==See also==
 
==See also==

Revision as of 11:09, 4 April 2018

NXP i.MX6 Quad

IMX6Quad Diagram.jpg

CPU Complex

Memory

DDR
  • 2x32 LP-DDR2, 1x64 DDR3 / LV-DDR3

NAND

  • SLC/MLC, 40-bit ECC, ONFI2.2, DDR

Connectivity

  • S-ATA and PHY

Advanced power management

PMU integration 

NXP PF100 power management unit

Package and temperature

  • 21 x 21mm, 0.8 mm BGA
  • Consumer (-20C to +105C), up to 1.2 GHz
  • Industrial (-40C to +105C), up to 800 MHz
  • Automotive (-40C to +125C), AEC-Q100, up to 1 GHz

Block diagram

Screenshot-2018-4-4 i MX 6Dual 6Quad Applications Processor for Consumer Products Data Sheet - IMX6DQCEC pdf(1).png

Documentation

See also