Difference between revisions of "IMX6 Quad"

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<u>'''Memory'''</u>
 
<u>'''Memory'''</u>
  
<div id="panel3" class="panel-collapse collapse in" role="tabpanel" aria-labelledby="headingOne" aria-expanded="true"><div class="toggle_container">DDR
+
<div id="panel3" class="panel-collapse collapse in" role="tabpanel" aria-labelledby="headingOne" aria-expanded="true">
* 2x32 LP-DDR2, 1x64 DDR3 / LV-DDR3
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* DDR
 
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** 2x32 LP-DDR2, 1x64 DDR3 / LV-DDR3
NAND
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* NAND
 
+
** SLC/MLC, 40-bit ECC, ONFI2.2, DDR
* SLC/MLC, 40-bit ECC, ONFI2.2, DDR
 
  
 
<u>'''Connectivity'''</u>
 
<u>'''Connectivity'''</u>
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* S-ATA and PHY
 
* S-ATA and PHY
  
</div>
 
 
</div>
 
</div>
 
<u>'''Advanced power management'''</u>
 
<u>'''Advanced power management'''</u>

Latest revision as of 12:02, 4 April 2018

NXP i.MX6 Quad

IMX6Quad Diagram.jpg

CPU Complex

Memory

  • DDR
    • 2x32 LP-DDR2, 1x64 DDR3 / LV-DDR3
  • NAND
    • SLC/MLC, 40-bit ECC, ONFI2.2, DDR

Connectivity

  • S-ATA and PHY

Advanced power management

Package and temperature

  • 21 x 21mm, 0.8 mm BGA
  • Consumer (-20C to +105C), up to 1.2 GHz
  • Industrial (-40C to +105C), up to 800 MHz
  • Automotive (-40C to +125C), AEC-Q100, up to 1 GHz

Block diagram

Screenshot-2018-4-4 i MX 6Dual 6Quad Applications Processor for Consumer Products Data Sheet - IMX6DQCEC pdf(1).png

Documentation

See also