Difference between revisions of "IMX6 Dual Lite"

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<u>'''Advanced power management'''</u>
 
<u>'''Advanced power management'''</u>
  
<div id="panel6" class="panel-collapse collapse in" role="tabpanel" aria-labelledby="headingOne"><div class="toggle_container">PMU integration </div>
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<div id="panel6" class="panel-collapse collapse in" role="tabpanel" aria-labelledby="headingOne">
[https://www.nxp.com/products/power-management/pmics/configurable-pmics-pf-series/14-channel-configurable-power-management-ic:MMPF0100 NXP PF100 power management unit]
+
* PMU integration 
 +
* [https://www.nxp.com/products/power-management/pmics/configurable-pmics-pf-series/14-channel-configurable-power-management-ic:MMPF0100 NXP PF100 power management unit]
  
 
</div>
 
</div>

Revision as of 11:14, 4 April 2018

NXP i.MX6 Dual_Lite

IMX6Dual Lite Diagrama.jpg

CPU Complex

Memory

DDR
  • 2x32 LP-DDR2, 1x64 DDR3 / LV-DDR3

NAND

  • SLC/MLC, 40-bit ECC, ONFI2.2, DDR

Advanced power management

Block diagram

Screenshot-2018-4-4 i MX 6Solo 6DualLite Applications Processors for Consumer Products Data Sheet - IMX6SDLCEC pdf(1).png

Documentation

See also