Difference between revisions of "IMX6 Dual Lite"

From IGEP - ISEE Wiki

Jump to: navigation, search
 
Line 10: Line 10:
 
<u>'''Memory'''</u>
 
<u>'''Memory'''</u>
  
<div id="panel3" class="panel-collapse collapse in" role="tabpanel" aria-labelledby="headingOne" aria-expanded="true"><div class="toggle_container">DDR
+
<div id="panel3" class="panel-collapse collapse in" role="tabpanel" aria-labelledby="headingOne" aria-expanded="true">
* 2x32 LP-DDR2, 1x64 DDR3 / LV-DDR3
+
* DDR
 +
** 2x32 LP-DDR2, 1x64 DDR3 / LV-DDR3
 +
* NAND
 +
** SLC/MLC, 40-bit ECC, ONFI2.2, DDR
  
NAND
 
 
* SLC/MLC, 40-bit ECC, ONFI2.2, DDR
 
 
</div>
 
 
</div>
 
</div>
 
<u>'''Advanced power management'''</u>
 
<u>'''Advanced power management'''</u>

Latest revision as of 12:01, 4 April 2018

NXP i.MX6 Dual_Lite

IMX6Dual Lite Diagrama.jpg

CPU Complex

Memory

  • DDR
    • 2x32 LP-DDR2, 1x64 DDR3 / LV-DDR3
  • NAND
    • SLC/MLC, 40-bit ECC, ONFI2.2, DDR

Advanced power management

Package and temperature

  • 21 x 21 0.8 mm BGA
  • Consumer (0C to +95C -20C to +105C or -20C to +105C), up to 1 GHz
  • Industrial (-40C to +105C), up to 800 MHz
  • Automotive (-40C to +125C)

Block diagram

Screenshot-2018-4-4 i MX 6Solo 6DualLite Applications Processors for Consumer Products Data Sheet - IMX6SDLCEC pdf(1).png

Documentation

See also