IGEP0040HardwareRABugs
From IGEP - ISEE Wiki
Contents
- 1 BUG ALL_00: (IMPORTANT) ICAPE gerbers fabrication are out of date
- 2 BUG ALL_01: (IMPORTANT) Missing 1V8 26MHz Oscillator
- 3 BUG ALL_02: Marvell flat cable connector mounted
- 4 BUG ALL_03: PRI_TRST is low, has no PU
- 5 BUG ALL_04: (IMPORTANT) Remove power bad resistors
- 6 BUG ALL_05: V_3P3 LDO has no delay sequence
BUG ALL_00: (IMPORTANT) ICAPE gerbers fabrication are out of date
INFO:: This design version has some issues (20150527) instead the last version (20150603): LEDs in BOT layer and CAN bad voltage level
WORKAROUND: Because these issues detected are not important. This protos can be used to test
BUG ALL_01: (IMPORTANT) Missing 1V8 26MHz Oscillator
INFO:: This clock is not mounted at proto first assembly. It is necessary to enable some PLL and other PXA2128 clock requirements.
WORKAROUND: Installed a 1V8 26MHz Oscillator with 50 ppm from "XTAL affaire box"
- Mount O1, R106, C276
RESULT:
- Tested with oscilloscope VCXO_IN signal
BUG ALL_02: Marvell flat cable connector mounted
WORKAROUND: Use a 1.27 mm header instead to allow get access to JTAG signals easier
- Mount JTAGB
- Umount JTAG
BUG ALL_03: PRI_TRST is low, has no PU
WORKAROUND: Use PU resistor to V_1P8 to pull high this signal. This resistors should be added to IGEP0040 layout. Need to check if this bug is important
BUG ALL_04: (IMPORTANT) Remove power bad resistors
INFO:: This resistors disables power sequence from power switch and LDOs to PXA2128
WORKAROUND: Disable this SMARC feature
- Umount: R971, R972, R973, R974 and R975
BUG ALL_05: V_3P3 LDO has no delay sequence
INFO: Need to check if this bug is important