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| − | === BUG ALL_00: (IMPORTANT) ICAPE gerbers fabrication are out of date===
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| − | '''INFO:''': This design version has some issues (20150527) instead the last version (20150603): LEDs in BOT layer and CAN bad voltage level
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| − | '''WORKAROUND:''' Because these issues detected are not important. This protos can be used to test
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| − | === BUG ALL_01: (IMPORTANT) Missing 1V8 26MHz Oscillator ===
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| − | '''INFO:''': This clock is not mounted at proto first assembly. It is necessary to enable some PLL and other PXA2128 clock requirements.
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| − | '''WORKAROUND:''' Installed a 1V8 26MHz Oscillator with 50 ppm from "XTAL affaire box"
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| − | - Mount O1, R106, C276
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| − | '''RESULT:'''
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| − | - Tested with oscilloscope VCXO_IN signal
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| − | === BUG ALL_02: Marvell flat cable connector mounted ===
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| − | '''WORKAROUND:''' Use a 1.27 mm header instead to allow get access to JTAG signals easier
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| − | - Mount JTAGB
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| − | - Umount JTAG
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| − | === BUG ALL_03: PRI_TRST is low, has no PU===
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| − | '''WORKAROUND:''' Use PU resistor to V_1P8 to pull high this signal. This resistors should be added to IGEP0040 layout. '''Need to check if this bug is important'''
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| − | === BUG ALL_04: (IMPORTANT) Remove power bad resistors===
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| − | '''INFO:''': This resistors disables power sequence from power switch and LDOs to PXA2128
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| − | '''WORKAROUND:''' Disable this SMARC feature
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| − | - Umount: R971, R972, R973, R974 and R975
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| − | ----
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| − | === BUG ALL_05: V_3P3 LDO has no delay sequence ===
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| − | '''INFO:''' '''Need to check if this bug is important'''
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