Difference between revisions of "IGEP0040HardwareRABugs"
From IGEP - ISEE Wiki
m |
m |
||
| Line 38: | Line 38: | ||
---- | ---- | ||
| − | |||
=== BUG ALL_05: V_3P3 LDO has no delay sequence === | === BUG ALL_05: V_3P3 LDO has no delay sequence === | ||
Revision as of 18:31, 6 August 2015
Contents
BUG ALL_01: (IMPORTANT) Missing 1V8 26MHz Oscillator
INFO:: This clock is not mounted at proto first assembly. It is necessary to enable some PLL and other PXA2128 clock subsystem.
WORKAROUND: Installed a 1V8 26MHz Oscillator with 50 ppm from "XTAL affaire box"
- Mount O1, R106, C276
RESULT:
- Tested with oscilloscope VCXO_IN signal
BUG ALL_02: Marvell flat connector mounted
WORKAROUND: Use a 1.27 mm header instead to allow get access to signals easier
- Mount JTAGB
- Umount JTAG
BUG ALL_03: PRI_TRST is low, has no PU
WORKAROUND: Use PU resistor to V_1P8 to pull high this signal. This resistors should be added to Layout. Need to check if this bug is important
BUG ALL_04: (IMPORTANT) Remove power bad resistors
INFO:: This resistors disables power sequence from power switch and LDOs to PXA2128
WORKAROUND: Disable this SMARC feature
- Umount: R971, R972, R973, R974 and R975
BUG ALL_05: V_3P3 LDO has no delay sequence
INFO:: Need to check if this bug is important
