From IGEP - ISEE Wiki

Revision as of 10:52, 22 March 2018 by Manel Caro (talk | contribs) (Created page with "__TOC__ =Texas Instruments [ DM3730]= '''500x344px''' '''<u>MPU Subsystem</u>''' * [http://dow...")

(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

Texas Instruments DM3730

custom diagram 1 DM3730-1.jpg

MPU Subsystem

High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem.

  • 800-MHz TMS320C64x+™ DSP Core
  • Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
  • Video Hardware Accelerators

POWERVR SGX™ Graphics Accelerator (SGX530 Imagination Technologies)

  • Tile Based Architecture delivering 10 MPoly/sec
  • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
  • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
  • Fine Grained Task Switching, Load Balancing, and Power Management
  • Programmable High Quality Image Anti-Aliasing

Fully Software-Compatible With C64x and ARM9™

Commercial and Extended Temperature Grades

Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core

  • Eight Highly Independent Functional Units
fbd sprs685d.png


See also