View source for How to adjust Hardware RTC clock

= Overview =

Real time clock (RTC) is a computer clock (most often in the form of an integrated circuit) that keeps track of the current time. RTCs are present in almost any electronic device which needs to keep accurate time. More general information [http://en.wikipedia.org/wiki/Real-time_clock here].<br> 

IGEP Boards have two RTC clocks, each one located at MPU and PMIC:

* '''RTC System clock''': system clock is controlled by MPU using its internal RTC peripheral. Every boot-up, the default firmware (/etc/init.d/hwclock.sh) copies the hardware clock data from /dev/rtc to system clock to keeps clock up to date.

* '''RTC Hardware clock''': hardware clock is controlled by PMIC using its internal RTC peripheral. RTC PMIC affords two behaviours:
** '''RTC battery is not used''': PMIC RTC peripheral keeps hardware clock alive when OS isn't running and power source is active. If the power source fails, the PMIC RTC peripheral will lose its clock.
** '''RTC battery is used''': PMIC RTC peripheral keeps hardware clock alive when OS isn't running and backup battery powers the backup state as far as the input voltage is high enough (at least 2 weeks into IGEPv2).

== Simplified RTC diagram ==

{| cellspacing="1" cellpadding="1" width="150" border="1" align="center"
|-
| [[Image:RTC diagram.png|800px|Block diagram from IGEP0033]]<br> 
|}

= Requirements =

This How-to has been tested with an IGEPv2 RC Board (DM3730 and TPS65950), steps used below can be slightly different for other boards:

* IGEPv2 with its power supply
* [[IGEP firmware Yocto]]
* Network cable with Internet acces
* PC

= Rectify clock drift=

IGEP Boards use as a source clock an external 32,768 kHz crystal. This passive component can add clock drifts due:

* General drift error
* Ambient temperature drift error
* Aging drift error
*   ...

Software tools can be used to compensate these errors. Once you tested your implementation add some rule to  [http://es.wikipedia.org/wiki/Cron_%28Unix%29 cron deamon] to automatize the process. Some available solutions are:

== Set the date and time via NTP  ==

If your board is connected to Internet regularly, this can be the most interesting workaround. The network time protocol (NTP) is the current widely accepted standard for synchronizing clocks over the Internet. NTP uses a hierarchical scheme in order to synchronize the clocks in the network.


=== ntpd  deamon ===
You should configure "/etc/ntp.conf" with appropriated Internet ntp server (for example: "server pool.ntp.org")

To force time synchronization, it could be used ntpd daemon with "-q" option (This behavior mimics that of the ntpdate(8) program)
<pre>ntpd -d -c /etc/ntp.conf -q</pre>

{{Message/Work in progress}}

=== (alternative) ntpdate  program ===

Ntpdate program is not installed into firmware by default, use zypper program to download and install the package: 

* Uninstall ntp deamon:
<pre>zypper rm ntp</pre>
* Install ntpdate
<pre>zypper in ntpdate</pre>

Once you finished it, make sure that IGEP is connected to Internet.

* Synchronize system clock and hardware clock with NTP server:

<pre>ntpdate pool.ntp.org; hwclock --systohc </pre>
<br> 
* Compare offset between ntp server and your system clock:

<pre>ntpdate -q pool.ntp.org && date </pre>

If the result is positive, it means that your system clock is delayed and viceversa.

== Rectify systematic error editing PMIC RTC registers ==
This workaround can be helpful when your board is not regularly connected to Internet. For this method we are going to:
* Calculate systematic clock error
* Rectify systematic clock error configuring PMIC RTC registers

===  Calculate systematic clock error ===

Each IGEP Board has its own systematic clock error. To guess it, Can be helpful use [http://labs.isee.biz/index.php/How_to_adjust_Hardware_RTC_clock#ntpdate__program ntpdate program] to calculate systematic clock error added every day:

* Synchronize your system clock using: ntpdate pool.ntp.org
* Compare actual offset (it is recommendable wait between one or two days to deprecate random errors produced by crystal and ntp synchronization): ntpdate -q pool.ntp.org && date

Finally, my IGEPv2 RC Board was a systematic drift of +3.6 seconds/day aprox.

=== Rectify systematic clock error configuring PMIC RTC registers ===

==== Overview ====
Now its time to compensated this delayed drift (+3.6 seconds/day) configuring PMIC RTC registers. The edited registers will be:
*RTC_CTRL_REG: Enables RTC compensation.
**I2c bus: I2C1
**Address: 0x4b
**Register: 0x29
*RTC_COMP_LSB_REG: 16 bits LSB of drift value (COM_REG) in ([http://en.wikipedia.org/wiki/Two%27s_complement Two's complement]).
**I2c bus: I2C1
**Address: 0x4b
**Register: 0x2c
*RTC_COMP_MSB_REG: 16 bits MSB of drift value (COM_REG) in ([http://en.wikipedia.org/wiki/Two%27s_complement Two's complement]).
**I2c bus: I2C1
**Address: 0x4b
**Register: 0x2d

==== Calculate COM_REG value ====
 
If autocompensation is enabled PMIC RTC peripheral will compensate every hour and 1 second the clock drift using the COMP_REG value, It adds or substract a second. The next formula shows how to calculate it:

[[File:Rtc formula.gif]]

Now pass your COMP_REG decimal value to hexadecimal, in my case was 0X1333 (4915).

==== Edit registers ====
Registers will be edited using the i2c-tools, these registers will be saved until RTC source is not active:
* Enable Hardware compensation:
<pre> i2cset -f -y 1 0x4b 0x29 0x05 </pre>
* Write RTC_COMP registers:
<pre>
i2cset -f -y 1 0x4b 0x2d 0x13
i2cset -f -y 1 0x4b 0x2c 0x33 </pre>
* Check register values:
<pre>i2cdump -y -f 1 0x4b </pre>

More information at [http://www.ti.com/litv/pdf/swcu050g TPS65950 TRM] section 3.4.2

==== Correct system clock ====

Hardware clock will be compensated automatically, to transfer hardware clock to system clock is necessary use hwclock command:

<pre> hwclock --hctosys</pre>