4,199
edits
Changes
m
* UART0{| align="JUSTIFY" cellpadding="1" border="1" style="width: 300px; height: 1px;"**|-| '''Name''' | '''SODIMM pin''' | '''AM335X pin''' |-| UART0_TX pin | 59 from SODIMM**| E16|-| UART0_RX pin | 60 from SODIMM**| E15|-| UART0_CTS pin | 61 from SODIMM**| E18|-| UART0_RTS pin | 62 from SODIMM* UART1| E17|-**| UART1_TX pin | 63 from SODIMM**| D15|-| UART1_RX pin | 64 from SODIMM**| D16|-| UART1_CTS pin | 65 from SODIMM**| D18|-| UART1_RTS pin | 66 from SODIMM* UART2| D17|-**| UART2_TX pin | 52 from SODIMM**| K18|-| UART2_RX pin | 53 from SODIMM* UART3| L18|-**| UART3_TX pin | 45 or | C15|-| UART3_TX| 54 from SODIMM**| L17|-| UART3_RX pin | 55 or | L16|-| UART3_RX| 74 from SODIMM* UART4| C18|-**| UART4_TX pin | 76 from SODIMM**| J18|-| UART4_RX pin | 81 from SODIMM* UART5| K15|-**| UART5_TX pin | 67 from SODIMM**| J17|-| UART5_RX pin | 68 from SODIMM**| H16|-| UART5_CTS pin | 97 from SODIMM**| G15|-| UART5_RTS pin | 96 from SODIMM| G16|}
→Optional UARTs
IGEP COM AQUILA contains six optional UARTs buses:
=== UART design notes ===