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<pre> 175 cpu_init_crit:
176 /*
177 * Invalidate L1 I/D
178 */
179 mov r0, #0 /* set up for MCR */
180 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
181 mcr p15, 0, r0, c7, c5, 1 /* invalidate icache */
182
183 /* Invalide L2 cache (gp device call point)
184 * - warning, this may have issues on EMU/HS devices
185 * this call can corrupt r0-r5
186 */
187 mov r12, #0x1 @ set up to invalide L2
188 smi: .word 0xE1600070 @ Call SMI monitor
189
190 /*
191 * disable MMU stuff and caches
192 */
193 mrc p15, 0, r0, c1, c0, 0
194 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
195 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
196 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
197 #ifndef CONFIG_ICACHE_OFF
198 orr r0, r0, #0x00001800 @ set bit 11,12 (---I Z---) BTB,I-Cache
199 #endif
200 mcr p15, 0, r0, c1, c0, 0
201
202 /*
203 * Jump to board specific initialization... The Mask ROM will have already initialized
204 * basic memory. Go here to bump up clock rate and handle wake up conditions.
205 */
206 adr r0, _start /* r0 <- current position of code */
207 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
208 cmp r0, r1 /* pass on info about skipping some init portions */
209 moveq r0,#0x1 /* flag to skip prcm and sdrc setup */
210 movne r0,#0x0
211
212 mov ip, lr /* persevere link reg across call */
213 bl lowlevel_init /* go setup pll,mux,memory */
214 mov lr, ip /* restore link */
215 mov pc, lr /* back to my caller */
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