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Peripherals Summary

110 bytes removed, 11:46, 20 April 2012
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= Overview =
This article wiki pretends introduce the capabilities of most used peripherals in IGEPv2IGEP Boards based in OMAP3530 and DM3730<br> = Feedback and Contributing = At any point, if you see a mistake you can contribute to this How-To.
= Peripherals =
=== UART ===
UART (universal asynchronous receiver/transmitter) converts parallel data from system bus to serial data through a port. At the destination, a second UART re-assembles this data. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms. External signals may be of many different forms.
IGEPv2 can handle RS232 and RS485 but not all pads have these standards, Omap UART peripheral use CMOS level voltage (1V8).
Omap 3530 have three UARTs and Omap 3730 (DM3730) have four UARTs. UART4 is not avaliable in IGEPv2, but IGEP MODULE can use it:.<br>  *gpmc_wait3/uart4_rx - J8 pin: UART4 Receive data (input) *gpmc_wait2/uart4_tx - K8 pin: UART4 Transmit data (output)
Omap UART peripheral uses can use four signals:
*UART TX: Transmit signal.
*UART RX: Receive signal.
*UART RTS: Ready to send, used in RS485 and hardware flow control.
*UART CTS: Clear to send, used in RS485 and hardware flow control.<br>
*The speed transmion data is mesured in bauds per second, for example: Kernel console params uses 115200 bps (equivalent to 14 Kbytes per second). The speed can set up from 300 bauds to 3686400 bauds.
More information:
*[http://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter http://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter]
*Supports DMA for data transfer operations, for reduce CPU usage.
*Supports full duplex data transfer operations, <span lang="en" classid="short_textresult_box" idclass="result_boxshort_text"><span class="hps">simultaneous comunication between master and slave.</span></span>
*Supports configuration of number of wordlength.
*Supports configuration of phase and polarity of the device functional clock for each channel.
=== BSP ===
BSP (Buffered Serial Port) named in Omap McBSP (Multichannel Buffered Serial Port). This port provides a full-duplex direct serial interface between the device and other devices in a system such as other application chips ([http://en.wikipedia.org/wiki/Baseband#Digital_baseband_transmission digital base band]), audio and voice codec (power management device), etc. Because of its high level of versatility, it can accommodate to a wide range of peripherals and clocked frame oriented protocols.
Omap have five BSP peripherals (McBSP1, McBSP2, McBSP3, McBSP4 and McBSP5). It can uses seven signals:<br>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - 1-bit or 4-bit transfer mode specifications for SD and SDIO cards
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; - 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards
=== I2C ===
I2C (Inter-Integrated Circuit) is a [http://en.wikipedia.org/wiki/Multi-master_bus multi-master] serial computer bus.  There are four I2C in Omap, but only three avaliable (I2C4 is used to comunicate with TPS65950). Omap I2C use CMOS&nbsp;voltage level (1V8) and implements two signals:
*SDA: Data. Open-drain output buffer. Requires external pullup resistor.
*SCL: Clock, master device generate it. Open-drain output buffer. Requires external pullup resistor. <br>
Their caracteristics characteristics are:<br>
*Compliance with Philips I2C specification version 2.1*Support for standard mode (up to 100K bits/s), fast mode (up to 400K bits/s) and HS mode for transfer up to 3.4M bits/s*Support for 3-wire/2-wire SCCB master mode for I2C2 and I2C3 modules, 2-wire SCCB master mode for I2C1 module, up to 100K bits/s*7-bit and 10-bit device addressing modes*Multimaster transmitter/slave receiver mode*Multimaster receiver/slave transmitter mode*Built-in FIFO for buffered read or write:*8 bytes for I2C1 and I2C2*64 bytes for I2C3*Module enable/disable capability*Programmable clock generation*8-bit-wide data access*Low-power consumption design*Two [http://en.wikipedia.org/wiki/Direct_memory_access DMA] channels
*Wide interrupt capability<br>
*[http://en.wikipedia.org/wiki/I%C2%B2C http://en.wikipedia.org/wiki/I%C2%B2C]
*[[How to use I2C]]<br>
 
 
[[Category:Peripherals]]
[[Category:Work in progress]]
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