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= Overview =
This article wiki pretends explain introduce the capabilities of most used peripherals in IGEPv2.IGEP Boards based in OMAP3530 and DM3730<br>
= Feedback and Contributing Peripherals = === UART === UART (universal asynchronous receiver/transmitter) converts parallel data from system bus to serial data through a port. At the destination, a second UART re-assembles this data. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms. External signals may be of many different forms. IGEPv2 can handle RS232 and RS485 but not all pads have these standards, Omap UART peripheral use CMOS level voltage (1V8). Omap 3530 have three UARTs and Omap 3730 (DM3730) have four UARTs. UART4 is not avaliable in IGEPv2, but IGEP MODULE can use it.<br>
*[http://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter http://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter] *[http://omappedia.org/wiki/Kernel_UART http://omappedia.org/wiki/Kernel_UART] *[[How to use UARTs]]
=== GPIO ===
GPIO (General Purpose Input/Output) is a generic pin on a chip whose behavior (including whether it is an input or output pin) can be controlled through software. Omap use CMOS voltage levels (1V8) and the pads are connected directly to it. Some Omap GPIO characteristics are:<br> *Set the data input and output direction. *Configure GPIO pin to high or low states. *Configure GPIO pins for interrupt control *Enable and disable interrupts *Enable and disable wakeup capability per GPIO pin. More information: *[http://en.wikipedia.org/wiki/GPIO http://en.wikipedia.org/wiki/GPIO] *[http://omappedia.org/wiki/GPIO http://omappedia.org/wiki/GPIO] *[[How to use GPIOs]] Example: [[What can I do with IGEP0020#How_to_handle_the_gpio-LED.27s]] <br>
=== SPI ===
SPI (Serial Peripheral Interface Bus) is a synchronous serial data link. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. It can be faster than I2C protocol and it is usually used in short distances, it uses CMOS level voltage (1V8). Omap have four SPIs: SPI1 supports up to four peripherals, SPI2 and SPI3 support up to two peripherals, and SPI4 supports only one peripheral. Omap SPI is named McSPI (Multichannel Serial Peripheral Interface Bus).Omap McSPI peripheral uses five signals: *McSPI_CSO: Chip Select 0. *McSPI_CS1: Chip Select 1. *McSPI_SOMI: Slave output master input data. *McSPI_SIMO: Slave input master output data. *McSPI_CLK: Clock.<br> Omap McSPI have the next characteristics: *Supports DMA for data transfer operations, for reduce CPU usage. *Supports full duplex data transfer operations, <span lang="en" id="result_box" class="short_text"><span class="hps">simultaneous comunication between master and slave.</span></span> *Supports configuration of number of wordlength. *Supports configuration of phase and polarity of the device functional clock for each channel. *Support configuration of the bitrate for each channel. Between 1.5 KHz and 48 MHz More information: *[http://omappedia.org/wiki/Kernel_McSPI http://omappedia.org/wiki/Kernel_McSPI] *[http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus]<br> *[[How to use SPI]]
=== BSP ===
=== MMC ===
=== I2C ===
I2C (Inter-Integrated Circuit) is a [http://en.wikipedia.org/wiki/Multi-master_bus multi-master] serial computer bus. There are four I2C in Omap, but only three avaliable (I2C4 is used to comunicate with TPS65950). Omap I2C use CMOS voltage level (1V8) and implements two signals: *SDA: Data. Open-drain output buffer. Requires external pullup resistor. *SCL: Clock, master device generate it. Open-drain output buffer. Requires external pullup resistor. <br> Their characteristics are:<br> *Compliance with Philips I2C specification version 2.1 *Support for standard mode (up to 100K bits/s), fast mode (up to 400K bits/s) and HS mode for transfer up to 3.4M bits/s *Support for 3-wire/2-wire SCCB master mode for I2C2 and I2C3 modules, 2-wire SCCB master mode for I2C1 module, up to 100K bits/s *7-bit and 10-bit device addressing modes *Multimaster transmitter/slave receiver mode *Multimaster receiver/slave transmitter mode *Built-in FIFO for buffered read or write: *8 bytes for I2C1 and I2C2 *64 bytes for I2C3 *Module enable/disable capability *Programmable clock generation *8-bit-wide data access *Low-power consumption design *Two [http://en.wikipedia.org/wiki/Direct_memory_access DMA] channels *Wide interrupt capability<br> More information: *[http://omappedia.org/wiki/Kernel_I2C http://omappedia.org/wiki/Kernel_I2C] *[http://en.wikipedia.org/wiki/I%C2%B2C http://en.wikipedia.org/wiki/I%C2%B2C] *[[How to use I2C]]<br> [[Category:Peripherals]][[Category:Work in progress]]