Difference between revisions of "OMAP3530"
From IGEP - ISEE Wiki
Manel Caro (talk | contribs) |
Manel Caro (talk | contribs) |
||
Line 1: | Line 1: | ||
− | = Texas Instruments OMAP3530 = | + | = Texas Instruments OMAP3530 = |
− | '''OMAP™ 3 Architecture''' | + | '''OMAP™ 3 Architecture''' |
− | '''<u>MPU Subsystem</u>''' | + | '''<u>MPU Subsystem</u>''' |
− | *Up to 720-MHz ARM Cortex™-A8 Core. | + | *Up to 720-MHz ARM Cortex™-A8 Core. |
*NEON™ SIMD Coprocessor | *NEON™ SIMD Coprocessor | ||
− | <u>'''High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem.'''</u> | + | <u>'''High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem.'''</u> |
− | *520-MHz TMS320C64x+™ DSP Core | + | *520-MHz TMS320C64x+™ DSP Core |
− | *Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels) | + | *Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels) |
*Video Hardware Accelerators | *Video Hardware Accelerators | ||
− | <u>'''POWERVR SGX™ Graphics Accelerator'''</u> (SGX530 Imagination Technologies) | + | <u>'''POWERVR SGX™ Graphics Accelerator'''</u> (SGX530 Imagination Technologies) |
− | *Tile Based Architecture delivering 10 MPoly/sec | + | *Tile Based Architecture delivering 10 MPoly/sec |
− | *Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality | + | *Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality |
− | *Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 | + | *Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 |
− | *Fine Grained Task Switching, Load Balancing, and Power Management | + | *Fine Grained Task Switching, Load Balancing, and Power Management |
*Programmable High Quality Image Anti-Aliasing | *Programmable High Quality Image Anti-Aliasing | ||
− | <u>'''Fully Software-Compatible With C64x and ARM9™'''</u> | + | <u>'''Fully Software-Compatible With C64x and ARM9™'''</u> |
− | <u>'''Commercial and Extended Temperature Grades'''</u><u>'''Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core'''</u> | + | <u>'''Commercial and Extended Temperature Grades'''</u> |
+ | |||
+ | <u</u><u>'''Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core'''</u> | ||
*Eight Highly Independent Functional Units | *Eight Highly Independent Functional Units | ||
[[Image:OMAP3530 bloques.jpg|center]] | [[Image:OMAP3530 bloques.jpg|center]] |
Revision as of 17:42, 18 April 2010
Texas Instruments OMAP3530
OMAP™ 3 Architecture
MPU Subsystem
- Up to 720-MHz ARM Cortex™-A8 Core.
- NEON™ SIMD Coprocessor
High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem.
- 520-MHz TMS320C64x+™ DSP Core
- Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
- Video Hardware Accelerators
POWERVR SGX™ Graphics Accelerator (SGX530 Imagination Technologies)
- Tile Based Architecture delivering 10 MPoly/sec
- Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
- Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
- Fine Grained Task Switching, Load Balancing, and Power Management
- Programmable High Quality Image Anti-Aliasing
Fully Software-Compatible With C64x and ARM9™
Commercial and Extended Temperature Grades
<u</u>Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units