Difference between revisions of "OMAP3530"
From IGEP - ISEE Wiki
| Line 37: | Line 37: | ||
[http://www.ti.com/litv/pdf/spruf98d OMAP3530 Hardware Reference Manual] | [http://www.ti.com/litv/pdf/spruf98d OMAP3530 Hardware Reference Manual] | ||
| − | [[Category:Hardware]] | + | [[Category:Hardware]] [[Category:IGEP0030]] [[Category:IGEP0020]] |
Revision as of 14:51, 28 July 2011
Texas Instruments OMAP3530
MPU Subsystem
- Up to 720-MHz ARM Cortex™-A8 Core ARMv7 Architecture.
- In-Order, Dual-Issue, Superscalar Microprocessor Core.
- NEON™ SIMD Coprocessor
High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem.
- 520-MHz TMS320C64x+™ DSP Core
- Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
- Video Hardware Accelerators
POWERVR SGX™ Graphics Accelerator (SGX530 Imagination Technologies)
- Tile Based Architecture delivering 10 MPoly/sec
- Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
- Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
- Fine Grained Task Switching, Load Balancing, and Power Management
- Programmable High Quality Image Anti-Aliasing
Fully Software-Compatible With C64x and ARM9™
Commercial and Extended Temperature Grades
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units
