Changes

IMX6 Quad

67 bytes removed, 12:02, 4 April 2018
no edit summary
'''<u>CPU Complex</u>'''
::* 4x [http://www.arm.com/ ARM] [https://developer.arm.com/products/processors/cortex-a/cortex-a9 Cortex-A9] up to 1.2 GHz::* [https://developer.arm.com/technologies/neon NEON SIMD media accelerator]
<u>'''Memory'''</u>
<div id="panel3" class="panel-collapse collapse in" role="tabpanel" aria-labelledby="headingOne" aria-expanded="true"><div class="toggle_container">* DDR** 2x32 LP-DDR2, 1x64 DDR3 / LV-DDR3 * NAND ** SLC/MLC, 40-bit ECC, ONFI2.2, DDR
<u>'''Connectivity'''</u>
* S-ATA and PHY
</div>
</div>
<u>'''Advanced power management'''</u>
<div id="panel6" class="panel-collapse collapse in" role="tabpanel" aria-labelledby="headingOne"><div class="toggle_container">* PMU integration </div>* [https://www.nxp.com/products/power-management/pmics/configurable-pmics-pf-series/14-channel-configurable-power-management-ic:MMPF0100 NXP PF100 power management unit]
<u>'''Package and temperature'''</u>
560
edits