Difference between revisions of "IMX6 Dual"
From IGEP - ISEE Wiki
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* [[IMX6 Dual Lite|Dual Lite]] | * [[IMX6 Dual Lite|Dual Lite]] | ||
* [[IMX6 Quad|Quad]] | * [[IMX6 Quad|Quad]] | ||
| + | * [https://www.nxp.com/video/:IMX6SERIES_VID i.MX 6 User Experience - Breaking Boundaries - Use Case] | ||
Revision as of 11:08, 4 April 2018
NXP i.MX6 Dual
CPU Complex
- 2x ARM Cortex-A9 up to 1.2 GHz
- NEON SIMD media accelerator
Memory
DDR
- 2x32 LP-DDR2, 1x64 DDR3 / LV-DDR3
NAND
- SLC/MLC, 40-bit ECC, ONFI2.2, DDR
Connectivity
- S-ATA and PHY
Advanced power management
PMU integration
Block diagram
Documentation
- i.MX 6Dual/6Quad Applications Processors for Consumer Products - Data Sheet
- i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors - Data Sheet
- i.MX 6Dual/6Quad Consumer-PoP Applications Processor Data Sheet
- i.MX 6Dual/6Quad Applications Processors for Industrial Products - Data Sheet
- IMX6DQ6SDLHDG, Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors
- i.MX 6 Series of Applications Processors Fact Sheet
- i.MX 6Dual/6Quad Applications Processor Reference Manual
- LDB Clock Switch Procedure & i.MX6 Asynchronous Clock Switching Guidelines
