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How to adjust Hardware RTC clock

2,035 bytes added, 22:11, 29 October 2017
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{{Message/Work in progress}}= Overview =Real time clock (RTC) is a computer clock (most often in the form of an integrated circuit) that keeps track of the current time. RTCs are present in almost any electronic device which needs to keep accurate time. More general information [http://en.wikipedia.org/wiki/Real-time_clock here].
Real time clock (IGEP Boards have two RTC) is a computer clock (most often in the form of an integrated circuit) that keeps track of the current time. RTCs are present in almost any electronic device which needs to keep accurate time. More general information [httpclocks, each one located at MPU and PMIC://en.wikipedia.org/wiki/Real-time_clock here].<br>
In IGEP Boards, * '''RTC System clock''': system clock is controlled by MPU and PMIC contains each one a using its internal RTC peripheral. Every boot-up, the default firmware (/etc/init.d/hwclock.sh) copies the hardware clock data from /dev/rtc to system clock to keeps clock:up to date.
* '''RTC System Hardware clock''': system hardware clock is controlled by OMAP processors PMIC using its internal RTC peripheral. Every bootupRTC PMIC affords two behaviours:** '''RTC battery is not used''': PMIC RTC peripheral keeps hardware clock alive when OS isn't running and power source is active. If the power source fails, the default firmware copies the hardware PMIC RTC peripheral will lose its clock data from /dev/rtc to system clock data to .** '''RTC battery is used''': PMIC RTC peripheral keeps hardware clock up to datealive when OS isn't running and backup battery powers the backup state as far as the input voltage is high enough (at least 2 weeks into IGEPv2).
* '''RTC Hardware clock''': hardware clock is controlled by PMIC IC using its internal RTC peripheral. RTC PMIC can afford two behaviours:** RTC battery is not used: PMIC RTC peripheral keeps hardware clock alive when OS isn't running and power source is active. If the power source fails, the RTC Hardware clock will lose its clock.** RTC battery is used: PMIC RTC peripheral keeps hardware clock alive when OS isn't running and backup battery powers the backup state as far as the input voltage is high enough. == Simplified RTC diagram == {| cellspacingborder="1" cellpaddingwidth="1150" widthcellspacing="1501" bordercellpadding="1" align="center"
|-
|| [[Image:RTC diagram.png|800px|Block diagram from IGEP0033]]<br>
|}
= Requirements = 
This How-to has been tested with an IGEPv2 RC Board (DM3730 and TPS65950), steps used below can be slightly different for other boards:
* IGEPv2 with its power supply
* [[IGEP firmware Yocto]]
* Network cablewith Internet acces
* PC
= Rectify clock drift=IGEP Boards use as a source clock an external 32,768 kHz crystal. This passive component can add clock drifts due:
IGEP Boards use as a source clock a 32* General drift error* Ambient temperature drift error* Aging drift error* ..768kHz crystal. This passive component can add clock drifts due:
*General drift error*Ambient temperature error*Aging error* Software tools can be used to compensate these errors.Once you tested your implementation add some rule to [http://es.wikipedia.org/wiki/Cron_%28Unix%29 cron deamon] to automatize the process. Some available solutions are:
Some software tools ==Set the date and time via NTP==If your board is connected to Internet regularly, this can be used to compensate these errors. Once you tested your implementation add some rule to [http://esthe most interesting workaround.wikipediaThe network time protocol (NTP) is the current widely accepted standard for synchronizing clocks over the Internet.org/wiki/Cron_%28Unix%29 cron deamon] NTP uses a hierarchical scheme in order to automatize itsynchronize the clocks in the network.
== Set the date and time via NTP ==
If your board its is connected to Internet, this can be the most interesting workaround. The network time protocol (NTP) is the current widely accepted standard for synchronizing clocks over the Internet. NTP uses a hierarchical scheme in order to synchronize the clocks in the network.
=== ntpdate program ntpd deamon===You should configure "/etc/ntp.conf" with appropriated Internet ntp server (for example: "server pool.ntp.org")
To force time synchronization, it could be used [http://manpages.ubuntu.com/manpages/maverick/man8/ntpd.8.html ntpd daemon with "-q" option] (This behavior mimics that of the ntpdate(8) program) <pre>ntpd -d -c /etc/ntp.conf -q</pre>===(alternative) ntpdate program===Ntpdate program is not installed into firmware by default, use zypper program to download and install the package:
* Uninstall ntp deamon:
 <pre> zypper rm ntp</pre>
* Install ntpdate
<pre>zypper in ntpdate </pre>
Once you installed the program, make sure that IGEP is connected to Internet.<pre>zypper in ntpdate</pre>
* Synchronize system clock and hardware clock:Once you finished it, make sure that IGEP is connected to Internet.
* Synchronize system clock and hardware clock with NTP server: <pre> ntpdate pool.ntp.org; hwclock --systohc </pre>
* Compare offset between ntp server and your system clock:
<pre> ntpdate -q pool.ntp.org && date </pre> If the result is positive, it means that your system clock is delayed and viceversa. ==Rectify systematic error editing PMIC RTC registers==This workaround can be helpful when your board is not regularly connected to Internet. For this method we are going to: * Calculate systematic clock error* Rectify systematic clock error configuring PMIC RTC registers ===Calculate systematic clock error===Each IGEP Board has its own systematic clock error. To guess it, Can be helpful use [http://labs.isee.biz/index.php/How_to_adjust_Hardware_RTC_clock#ntpdate__program ntpdate program] to calculate systematic clock error added every day:
If your result is positive, it means that * Synchronize your system clock using: ntpdate pool.ntp.org* Compare actual offset (it is delayed recommendable wait between one or two days to deprecate random errors produced by crystal and viceversantp synchronization): ntpdate -q pool.ntp.org && date
=== ntpd deamon ===Finally, my IGEPv2 RC Board was a systematic drift of +3.6 seconds/day aprox.
'''Under contruction'''===Rectify systematic clock error configuring PMIC RTC registers=======Overview====Now its time to compensated this delayed drift (+3.6 seconds/day) configuring PMIC RTC registers. The edited registers will be:
* RTC_CTRL_REG: Enables RTC compensation.** I2c bus: I2C1** Address: 0x4b** Register: 0x29* RTC_COMP_LSB_REG: 16 bits LSB of drift value (COM_REG) in ([http://en.wikipedia.org/wiki/Two%27s_complement Two's complement]).** I2c bus: I2C1** Address: 0x4b** Register: 0x2c* RTC_COMP_MSB_REG: 16 bits MSB of drift value (COM_REG) in ([http://en.wikipedia.org/wiki/Two%27s_complement Two's complement]).** I2c bus: I2C1** Address: 0x4b** Register: 0x2d == Rectify systematic error editing ==Calculate COM_REG value====If autocompensation is enabled PMIC RTC peripheral will compensate every hour and 1 second the clock drift using the COMP_REG value, It adds or substract a second. The next formula shows how to calculate it: [[File:Rtc formula.gif]] Now pass your COMP_REG decimal value to hexadecimal, in my case was 0X1333 (4915). ====Edit registers ====This workaround can Registers will be edited using the i2c-tools, these registers will be helpful when your board saved until RTC source is not connected to Internet. Using this method we are going toactive: * Calculate systematic clock errorEnable Hardware compensation: <pre> i2cset -f -y 1 0x4b 0x29 0x05 </pre>* Rectify systematic error using PMIC RTC Write RTC_COMP registers:
=== Calculate systematic clock error ===<pre>i2cset -f -y 1 0x4b 0x2d 0x13i2cset -f -y 1 0x4b 0x2c 0x33 </pre>* Check register values:
Every IGEP Board has its own systematic clock error. To find it, we use use [http:<pre>i2cdump -y -f 1 0x4b <//labs.isee.biz/index.php/How_to_adjust_Hardware_RTC_clock#ntpdate__program ntpdate program] to calculate the clock offset added every day:pre>
* Syncronize your system clock usingMore information at [http: ntpdate pool//www.ntpti.org* Compare actual offset (it is recommendable wait one or two days to deprecate random clock errors): ntpdate -q poolcom/litv/pdf/swcu050g TPS65950 TRM] section 3.ntp4.org && date2
My IGEP Board was a systematic drift of +3.6 seconds/day aprox.====Correct system clock====Hardware clock will be compensated automatically, to transfer hardware clock to system clock is necessary use hwclock command:
=== Rectify systematic error using PMIC RTC registers ===<pre> hwclock --hctosys</pre>
Using as a reference +3.6 seconds/day, now its time to compensated this delayed drift configuring PMIC [[Category:RTC registers.]]
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