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* '''RTC System Hardware clock''': system hardware clock is controlled by OMAP processors PMIC using its internal RTC peripheral. Every bootupRTC PMIC affords two behaviours:** '''RTC battery is not used''': PMIC RTC peripheral keeps hardware clock alive when OS isn't running and power source is active. If the power source fails, the default firmware copies the hardware PMIC RTC peripheral will lose its clock data from /dev/rtc to system clock data to .** '''RTC battery is used''': PMIC RTC peripheral keeps hardware clock up to datealive when OS isn't running and backup battery powers the backup state as far as the input voltage is high enough (at least 2 weeks into IGEPv2).
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|| [[Image:RTC diagram.png|800px|Block diagram from IGEP0033]]<br>
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= Requirements =
This How-to has been tested with an IGEPv2 RC Board (DM3730 and TPS65950), steps used below can be slightly different for other boards:
* IGEPv2 with its power supply
* [[IGEP firmware Yocto]]
* Network cablewith Internet acces
* PC
= Rectify clock drift=IGEP Boards use as a source clock an external 32,768 kHz crystal. This passive component can add clock drifts due: * General drift error* Ambient temperature drift error* Aging drift error* ...
<pre>ntpd -d -c /etc/ntp.conf -q</pre>===(alternative) ntpdate program===Ntpdate program is not installed into firmware by default, use zypper program to download and install the package:
* Uninstall ntp deamon:
<pre> zypper rm ntp</pre>
* Install ntpdate
* Synchronize system clock and hardware clock with NTP server: <pre> ntpdate pool.ntp.org; hwclock --systohc </pre>
* Compare offset between ntp server and your system clock:
<pre> ntpdate -q pool.ntp.org && date </pre>
If your the result is positive, it means that your system clock is delayed and viceversa.
=== ntpd deamon =Rectify systematic error editing PMIC RTC registers==This workaround can be helpful when your board is not regularly connected to Internet. For this method we are going to:
== Rectify =Calculate systematic clock error editing PMIC RTC registers ===This workaround can Each IGEP Board has its own systematic clock error. To guess it, Can be helpful when use [http://labs.isee.biz/index.php/How_to_adjust_Hardware_RTC_clock#ntpdate__program ntpdate program] to calculate systematic clock error added every day: * Synchronize your board system clock using: ntpdate pool.ntp.org* Compare actual offset (it is not connected recommendable wait between one or two days to Internetdeprecate random errors produced by crystal and ntp synchronization): ntpdate -q pool. Using ntp.org && date Finally, my IGEPv2 RC Board was a systematic drift of +3.6 seconds/day aprox. ===Rectify systematic clock error configuring PMIC RTC registers=======Overview====Now its time to compensated this method we are going todelayed drift (+3.6 seconds/day) configuring PMIC RTC registers. The edited registers will be: * RTC_CTRL_REG: Enables RTC compensation.** I2c bus: I2C1** Address: 0x4b** Register: 0x29* RTC_COMP_LSB_REG: 16 bits LSB of drift value (COM_REG) in ([http://en.wikipedia.org/wiki/Two%27s_complement Two's complement]).** I2c bus: I2C1** Address: 0x4b** Register: 0x2c* RTC_COMP_MSB_REG: 16 bits MSB of drift value (COM_REG) in ([http://en.wikipedia.org/wiki/Two%27s_complement Two's complement]).** I2c bus: I2C1** Address:0x4b* * Register: 0x2d ====Calculate systematic COM_REG value====If autocompensation is enabled PMIC RTC peripheral will compensate every hour and 1 second the clock errordrift using the COMP_REG value, It adds or substract a second. The next formula shows how to calculate it: [[File:Rtc formula.gif]] Now pass your COMP_REG decimal value to hexadecimal, in my case was 0X1333 (4915). ====Edit registers====* Rectify systematic error Registers will be edited using PMIC the i2c-tools, these registers will be saved until RTC source is not active: * Enable Hardware compensation: <pre> i2cset -f -y 1 0x4b 0x29 0x05 </pre>* Write RTC_COMP registers: <pre>i2cset -f -y 1 0x4b 0x2d 0x13i2cset -f -y 1 0x4b 0x2c 0x33 </pre>* Check register values: <pre>i2cdump -y -f 1 0x4b </pre> More information at [http://www.ti.com/litv/pdf/swcu050g TPS65950 TRM] section 3.4.2
=== Calculate systematic =Correct system clock error ====Hardware clock will be compensated automatically, to transfer hardware clock to system clock is necessary use hwclock command:
