Personal tools

Log in

Changes

From IGEP - ISEE Wiki

Jump to: navigation, search

Getting started with IGEP COM AQUILA

270 bytes added, 12:04, 7 November 2013
m
USB design rules
* For USB data lines: USB1 (USBH_DM and USBH_DP) and USB0 (USBOTG_DM and USBOTG_DP)
**Maintain symmetry 90R +/- 15% differential impedance in the layout traces.**Equal length and symmetric with regards of shape, length, and isolate via count. **Isolate differential pairs from nearby signals and circuitry to mantain maintain the signal integrity.* VBUS overcurrent protection: USB power source current must not be pass 500mA, you should apply a protection into the baseboard. [{{#lst:Template:Links|IGEP_AQUILA_EXPANSION_ISEE_Schematic}} IGEP AQUILA EXPANSION Public Schematic Schematics] proposes a solution using TPS2051D IC.* IGEP COM AQUILA includes into each USB peripheral a VBUS overvoltage protector.
== I2C ==
4,199
edits