Changes

Firsts steps with AM335x

2,454 bytes added, 19:54, 18 March 2013

→‎EMIF Timmings

= Board support package =

= Recovery = U-boot ==

# * '''src:''' http://git.isee.biz/?p=pub/scm/u-boot-arm.git;a=shortlog;h=refs/heads/master-am33x == Kernel == * '''src:''' http://git.isee.biz/?p=pub/scm/linux-omap-2.6.git;a=shortlog;h=refs/heads/linux-3.2.y-am335x = ANNEX = == UART recovery boot == 1. Make sure the BOOT mode is set to UART.# 2. Connect to the debug UART with your computer and launch the serial terminal application

picocom -b 115200 /dev/ttyUSB0 --send-cmd "sz -vv -X" --receive-cmd "rz -vv -X"

# 3. Start the board. When "CCCC" characters appear on terminal window, do:

C-a C-s

*** file: spl/u-boot-spl.bin# 4. Exit from picocom using C-a C-q, and relaunch picocom with

picocom -b 115200 /dev/ttyUSB0 --send-cmd "sz -vv -Y" --receive-cmd "rz -vv -Y"

# 5. When "CCCC" characters appear on terminal window, do:

C-a C-s

*** file: u-boot.binimg# 6. Hitting any key to stop automatic boot, should present the U-Boot prompt. == EMIF Timings == * http://processors.wiki.ti.com/index.php/AM335x_DDR_PHY_register_configuration_for_DDR3 '''K4B2G1646E-BIH9 : EMIF Parameters. Refer the EMIF register documentation and the memory datasheet for details''' * For 303 MHz m_clk 3.3ns  28-25 reg_t_rp 4 - 13.5ns 24-21 reg_t_rcd 4 - 13.5ns 20-17 reg_t_wr 4 - 15ns 16-12 reg_t_ras 10 - 36ns 11-6 reg_t_rc 15 - 49.5ns 5-3 reg_t_rrd 4 2-0 reg_t_wtr 4 EMIF_TIM1 000 00100 00100 0100 01010 001110 011 011 EMIF_TIM1 0x0888A39B  30-28 reg_t_xp 3 - 3nCK 27-25 reg_t_odt 5 - 6nCK 24-16 reg_t_xsnr 4 - 5nCK 15-6 reg_t_xsrd 4 - 5nCK 5-3 reg_t_rtp 3 - 4nCK 2-0 reg_t_cke 2 - 3nCK EMIF_TIM2 0 010 101 000000100 0000000100 011 010 EMIF_TIM2 0x2A04011A  31-28 reg_t_pdll_ul 5 27-21 reg_t_ckesr 0 20-15 reg_zq_zqcs 63 - 64nCK 14-13 reg_t_tdqsckmax 0 12-4 reg_t_rfc 32 - 107ns 3-0 reg_t_ras_max 15 EMIF_TIM3 0101 000000000 111111 00 000100000 1111 EMIF_TIM3 0x501F820F  31 reg_initref_dis 0 Initialization 30 Reserved 0 29 reg_srt 0 extended temp. 28 reg_asr 0 manual Self Refresh 27 Reserved 0 26-24 reg_pasr 0 23-16 Reserved 0 15-0 reg_refresh_rate 3B9 EMIF_SDREF 0 0 0 0 0 000 00000000 3B9 EMIF_SDREF 0x000003B9   31-29 reg_sdram_type 3 - DDR3 28-27 reg_ibank_pos 0 26-24 reg_ddr_term 2 - RZQ/2 23 reg_ddr2_ddqs 1 - differential DQS 22-21 reg_dyn_odt 1 - Dynamic ODT RZQ/4 20 reg_ddr_disable_dll 0 - enable DLL 19-18 reg_sdram_drive 1 - drive strength RZQ/7 17-16 reg_cwl 2 - CAS write latency 7 15-14 reg_narrow_mode 1 - 16-bit data bus width 13-10 reg_cl 10 - CAS latency of 9 9-7 reg_rowsize 5 - 14 row bits 6-4 reg_ibank 3 - 8 banks 3 reg_ebank 0 - 1 chip select 2-0 reg_pagesize 2 - 10 column bits EMIF_SDCFG 0011 00 010 1 01 0 01 10 01 1010 101 011 0 010 EMIF_SDCFG 0x61C24AB2

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