<br> One pad configuration register field is available for each pin. Each 32-bit pad configuration register is grouped into two 16-bit pad configuration register fields. One pad configuration register provides control for two different pins. These registers can be accessed using 8, 16 and 32 bits operations.<br>
The functional bits of a pad configuration register field are divided into the following five fields: • MUXMODE (3 bits) defines the multiplexing mode applied to the pin. A mode corresponds to the selection of the functionality mapped on the pin with six (0 to 5) possible functional modes for each pin. • PULL (2 bits) for combinational pullup/pulldown configuration:
– PULLTYPESELECT: Pullup/pulldown -> MUXMODE (3 bits) defines the multiplexing mode applied to the pin. A mode corresponds to the selection for of the functionality mapped on the pin. – PULLUDENABLE: Pullup/pulldown enable with six (0 to 5) possible functional modes for the each pin.
• INPUTENABLE -> PULL (1 bit2 bits) drives an input enable signal to the Ifor combinational pullup/O CTRL. pulldown configuration:
– INPUTENABLE = 0 - PULLTYPESELECT: Input Disable. Pin is configured in output only modePullup/pulldown selection for the pin. – INPUTENABLE = 1 - PULLUDENABLE: Input Enable. Pin is configured in bidirectional modePullup/pulldown enable for the pin.
• -> INPUTENABLE (1 bit) drives an input enable signal to the I/O CTRL. - INPUTENABLE = 0: Input Disable. Pin is configured in output only mode. - INPUTENABLE = 1: Input Enable. Pin is configured in bidirectional mode. -> Off mode values (5 bits) override the pin state when the OFFENABLE bit CONTROL.
CONTROL_PADCONF_X is set and off mode is active. This feature allows having separate configurations for the pins when in off mode: