From IGEP - ISEE Wiki
This wiki pretends introduce the capabilities of most used peripherals in IGEP Boards based in OMAP3530 and DM3730
UART (universal asynchronous receiver/transmitter) converts parallel data from system bus to serial data through a port. At the destination, a second UART re-assembles this data. Each UART contains a shift register which is the fundamental method of conversion between serial and parallel forms. External signals may be of many different forms.
IGEPv2 can handle RS232 and RS485 but not all pads have these standards, Omap UART peripheral use CMOS level voltage (1V8).
Omap 3530 have three UARTs and Omap 3730 (DM3730) have four UARTs. UART4 is not avaliable in IGEPv2, but IGEP MODULE can use it.
Omap UART peripheral can use four signals:
- UART TX: Transmit signal.
- UART RX: Receive signal.
- UART RTS: Ready to send, used in RS485 and hardware flow control.
- UART CTS: Clear to send, used in RS485 and hardware flow control.
Omap UART characteristics:
- 64-byte FIFO for receiver and 64-byte FIFO for transmitter
- Programmable interrupt trigger levels for FIFOs
- Configurable data format
- Data bit: 5, 6, 7, or 8 bits
- Parity bit: Even, odd, none
- Stop-bit: 1, 1.5, 2 bit(s)
- Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
- Supports DMA Mode for all UARTs.
- The speed transmion data is mesured in bauds per second, for example: Kernel console params uses 115200 bps (equivalent to 14 Kbytes per second). The speed can set up from 300 bauds to 3686400 bauds.
- How to use UARTs
GPIO (General Purpose Input/Output) is a generic pin on a chip whose behavior (including whether it is an input or output pin) can be controlled through software. Omap use CMOS voltage levels (1V8) and the pads are connected directly to it. Some Omap GPIO characteristics are:
- Set the data input and output direction.
- Configure GPIO pin to high or low states.
- Configure GPIO pins for interrupt control
- Enable and disable interrupts
- Enable and disable wakeup capability per GPIO pin.
SPI (Serial Peripheral Interface Bus) is a synchronous serial data link. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. It can be faster than I2C protocol and it is usually used in short distances, it uses CMOS level voltage (1V8).
Omap have four SPIs: SPI1 supports up to four peripherals, SPI2 and SPI3 support up to two peripherals, and SPI4 supports only one peripheral. Omap SPI is named McSPI (Multichannel Serial Peripheral Interface Bus).Omap McSPI peripheral uses five signals:
- McSPI_CSO: Chip Select 0.
- McSPI_CS1: Chip Select 1.
- McSPI_SOMI: Slave output master input data.
- McSPI_SIMO: Slave input master output data.
- McSPI_CLK: Clock.
Omap McSPI have the next characteristics:
- Supports DMA for data transfer operations, for reduce CPU usage.
- Supports full duplex data transfer operations, simultaneous comunication between master and slave.
- Supports configuration of number of wordlength.
- Supports configuration of phase and polarity of the device functional clock for each channel.
- Support configuration of the bitrate for each channel. Between 1.5 KHz and 48 MHz
- How to use SPI
BSP (Buffered Serial Port) named in Omap McBSP (Multichannel Buffered Serial Port). This port provides a full-duplex direct serial interface between the device and other devices in a system such as other application chips (digital base band), audio and voice codec (power management device), etc. Because of its high level of versatility, it can accommodate to a wide range of peripherals and clocked frame oriented protocols.
Omap have five BSP peripherals (McBSP1, McBSP2, McBSP3, McBSP4 and McBSP5). It can uses seven signals:
- McBSP_DX: Transmited serial data.
- McBSP_CLKX: Transmit serial clock.
- McBSP_FSX: Transmit frame syncronization.
- McBSP_DR: Received serial data.
- McBSP_CLKR: Received serial clock. Only in MCBSP1.
- McBSP_FSR:Received frame syncronization. Only in MCBSP1.
- McBSP_CLKS: External clock (shared by all McBSP modules).
List of recommended usage (non exhaustive) per McBSP modules in the device:
- McBSP1: Digital baseband (DBB) Data
- McBSP2: Audio data with audio buffer and SIDETONE feature
- McBSP3: Bluetooth voice data with SIDETONE feature
- McBSP4: DBB voice data
- McBSP5: Midi data
MMC (Multimedia Controller) is peripheral than can manage SD/MMC/SDIO , but other peripherals can be controled with this interface like WIFI. The MMC/SD/SDIO host controller deals with MMC/SD/SDIO protocol at transmission level, data packing, adding cyclic redundancy checks (CRC), start/end bit, and checking for syntactical correctness. Data transfers between the MMC controller and a memory card can use one bidirectional data line (for the MMC protocol) or four parallel data lines (for the SD protocol).
There are three MMC peripherals (MMC1, MMC2 and MMC3) and their use CMOS voltage levels (1V8). It can uses ten signals:
- MMC_DAT7: SD/MMC data pin 7.
- MMC_DAT6: SD/MMC data pin 6.
- MMC_DAT5: SD/MMC data pin 5.
- MMC_DAT4: SD/MMC data pin 4.
- MMC_DAT3: SD/MMC data pin 3. Used in SD card default data mode.
- MMC_DAT2: SD/MMC data pin 2. Used in SD card default data mode.
- MMC_DAT1: SD/MMC data pin 1. Used in SD card default data mode.
- MMC_DAT0: SD/MMC data pin 0. Used in MMC and SD card default data mode.
- MMC_CMD: SD/MMC command signal.
- MMC_CLK0: SD/MMC clock signal.
Some especifications are:
- Full compliance with MMC command/response sets as defined in the Multimedia Card System Specification, v4.2 including high-capacity (size > 2GB) cards HC MMC.
- Full compliance with SD command/response sets as defined in the SD Memory Card Specifications, v2.0 including high-capacity SDHC cards up to 32GB.
- Full compliance with SDIO command/response sets and interrupt/read-wait mode as defined in the SDIO Card Specification, Part E1, v2.00
- Full compliance with sets as defined in the SD Card Specification, Part A2, SD Host Controller Standard Specification, v2.00
- Full compliance with MMC bus testing procedure as defined in the Multimedia Card System Specification, v4.2
- Full compliance with CE-ATA command/response sets as defined in the CE-ATA Standard Specification
- Built-in 1024-byte buffer for read or write
- 32-bit-wide access bus to maximize bus throughput
- Designed for low power
- Programmable clock generation
- Support SDIO Read Wait and Suspend/Resume functions
- 1-bit or 4-bit transfer mode specifications for SD and SDIO cards
- 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards
I2C (Inter-Integrated Circuit) is a multi-master serial computer bus.
There are four I2C in Omap, but only three avaliable (I2C4 is used to comunicate with TPS65950). Omap I2C use CMOS voltage level (1V8) and implements two signals:
- SDA: Data. Open-drain output buffer. Requires external pullup resistor.
- SCL: Clock, master device generate it. Open-drain output buffer. Requires external pullup resistor.
Their characteristics are:
- Compliance with Philips I2C specification version 2.1
- Support for standard mode (up to 100K bits/s), fast mode (up to 400K bits/s) and HS mode for transfer up to 3.4M bits/s
- Support for 3-wire/2-wire SCCB master mode for I2C2 and I2C3 modules, 2-wire SCCB master mode for I2C1 module, up to 100K bits/s
- 7-bit and 10-bit device addressing modes
- Multimaster transmitter/slave receiver mode
- Multimaster receiver/slave transmitter mode
- Built-in FIFO for buffered read or write:
- 8 bytes for I2C1 and I2C2
- 64 bytes for I2C3
- Module enable/disable capability
- Programmable clock generation
- 8-bit-wide data access
- Low-power consumption design
- Two DMA channels
- Wide interrupt capability